HBM2E: The E Stands for Evolutionary
Samsung introduced the first memory products in March that conform to JEDEC’s HBM2E specification, but so far nothing has come to market—a reflection of just how difficult it is to manufacture this...
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Advanced Packaging Options Increase
Designing, integrating and assembling heterogeneous packages from blocks developed at any process node or cost point is proving to be far more difficult than expected, particularly where high...
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EDA Gears Up For 3D
Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor...
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New Technologies To Support 3D-ICs
Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor...
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The Race For Better Computational Software
Anirudh Devgan, president of Cadence, sat down with Semiconductor Engineering to talk about computational software, why it’s so critical at the edge and in AI systems, and where the big changes are...
View Article3D Power Delivery
Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels. The problems may even...
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The Race To Next-Gen 2.5D/3D Packages
Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing...
View ArticleDriving With Chiplets
The first examples of the upper class of vehicles that can drive autonomously on the highway already have arrived on the market or will be introduced to the market in the coming years. Travel on the...
View ArticleSurvival Of The Cheapest?
We all want the best solution to win, but that rarely happens. History is littered with products that were superior to the alternatives and yet lost out to a lessor rival. I am sure several examples...
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What’s The Best Advanced Packaging Option?
As traditional chip designs become more unwieldy and expensive at each node, many IC vendors are exploring or pursuing alternative approaches using advanced packaging. The problem is there are too many...
View ArticleMigrating 3D Into The Mainstream
Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for ANSYS’ Semiconductor...
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Planning For Panel-Level Fan-out
Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a...
View ArticleIs There A Crossover Point For Mainstream Anymore?
Until 28nm, it was generally assumed that process nodes would go mainstream one or two generations after they were introduced. So by the time the leading edge chips for smartphones and servers were...
View ArticleDesigning In 4D
The chip design world is no longer flat or static, and increasingly it’s no longer standardized. Until 16/14nm, most design engineers viewed the world in two dimensions. Circuits were laid out along x...
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What’s Next For High Bandwidth Memory
A surge in data is driving the need for new IC package types with more and faster memory in high-end systems. But there are a multitude of challenges on the memory, packaging and other fronts. In...
View ArticleNew Packaging Roadmap
Historically, the electronics industry has drawn sharp distinctions between the integrated circuit chip, the package that protects it from the environment, and the board that connects it to other...
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What Worked, What Didn’t In 2019
2019 has been a tough year for semiconductor companies from a revenue standpoint, especially for memory companies. On the other hand, the EDA industry has seen another robust growth year. A significant...
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Making 3D Structures And Packages More Reliable
The move to smaller vertical structures and complex packaging schemes is straining existing testing approaches, particularly in heterogeneous combinations on a single chip and in multi-die packages....
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5/3nm Wars Begin
Several foundries are ramping up their new 5nm processes in the market, but now customers must decide whether to design their next chips around the current transistor type or move to a different one at...
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Chiplet Momentum Rising
The chiplet model is gaining momentum as an alternative to developing monolithic ASIC designs, which are becoming more complex and expensive at each node. Several companies and industry groups are...
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