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Multi-Die Assemblies Dominate At 2nm And Below
Key Takeaways: Orders of magnitude performance improvements required for AI cannot happen without multi-die assemblies, new packaging options, and the underlying technologies and methodologies to...
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Managing Thermal Expansion And Electromigration Through Interposer Design
Key Takeaways: To increase interconnect density to support the bandwidth requirements of AI workloads, manufacturers are turning to 2.5D and 3D packaging architectures. While 2.5D interposers, as...
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Realizing The Future Of 3D-IC: Final Scenario And Sign-off
By Keith Felton and Todd Burkholder Multi-chiplet packages contain thousands of connections between chiplets, interposers, and package BGAs. After optimizing this complex connectivity, designers must...
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Making On-Chip Photonics Manufacturable
Key Takeaways: System-level energy and bandwidth pressures are pulling optics into the package faster than the manufacturing flow can mature. Photonics combines front-end fabrication, materials,...
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Chiplets Need A New Workflow
Key Takeaways: Chiplet design turns semiconductor development into a system-level problem, requiring coordinated workflows across design, packaging, verification, test, and reliability. Successful...
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Powering AI At Scale: Why 3D-ICs Demand A New Approach To Power Integrity
By Muhammad Hassan and Sudarshan Deo The semiconductor industry is undergoing a fundamental transition. Performance scaling is no longer driven primarily by transistor density, but by advanced...
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2.5D + 3D = “3.5D”!
The semiconductor industry is no longer defined solely by transistor scaling. As Moore’s law decelerates, advanced packaging has become the primary lever for achieving system-level performance gains....
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Power Integrity Without Blind Spots: A System Level Approach To 3D-ICs
Power delivery has become one of the defining challenges of next-generation semiconductor systems. As AI, high-performance computing, and data-centric workloads drive higher performance and tighter...
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Beating The Heat In 3D Packages
Key Takeaways: Thermal management is a central design constraint, requiring early, thorough planning. Accurate thermal simulation requires AI-driven adaptive meshing and real-world validation....
View ArticleSystem-level Reliability Verification for 2.5D/3D ICs Using Innovator3D IC...
The increasing demand for higher performance, lower power, and greater functionality in smaller packages has driven the rapid adoption of 2.5D and 3D Integrated Circuits (ICs). However, the inherent...
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Catching Critical Defects In TSVs And Stacked Chips
Key Takeaways Variation is becoming a bigger problem in multi-die assemblies with TSVs and hybrid bonding. Multi-modal approaches are required to test these devices. AI plays a role in improving defect...
View ArticleWhy Move To 2nm?
Key Takeaways: Scaling digital logic still provides significant benefits, especially lower power. Multi-die assemblies will be the predominant approach, and most of the circuitry will not be 2nm or...
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Chiplet Fundamentals For Engineers: eBook
Multi-die assemblies are the next phase of Moore’s Law, scaling up and out to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the...
View ArticleReliability And Traceability In Advanced Packages
The move from planar SoCs to advanced packages can improve performance and provide flexibility in large designs, which are difficult to fit onto a single reticle-sized die. But ensuring the device...
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When To Move To Multi-Die Assemblies
As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it’s often not feasible to fit everything onto a single planar die. But determining when to...
View ArticleThermal Modeling in Emerging Heterogeneous 2.5D/3D Systems (EPFL, Universidad...
A new technical paper titled “3D-ICE 4.0: Accurate and efficient thermal modeling for 2.5D/3D heterogeneous chiplet systems” was published by researchers at EPFL and Universidad Complutense de Madrid....
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What’s Next for 2.5D Packaging?
Interposers and bridges, two of the key elements for interconnecting multiple chips and chiplets in an advanced package, are undergoing fundamental changes in how they’re built and assembled....
View ArticleNew Approaches To Limit Cyberattacks On Hardware
The number and value of cyberattacks on semiconductors is rising, but new approaches to designing and packaging chips could put a significant dent in those figures. Semiconductor-related cybersecurity...
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How To Cool 3D-ICs
Experts at the Table: Semiconductor Engineering sat down to discuss how to cool 3D-ICs and what’s missing from the tool chain today, with John Ferguson, senior director of product management at Siemens...
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First Forays Into True 3D-IC Designs
Experts at the Table: Semiconductor Engineering sat down to discuss initial forays into 3D-ICs and what problems early adopters will encounter, with John Ferguson, senior director of product management...
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